Consumer electronic devices, such as cell phones, digital music players, and other handheld devices, run increasingly complicated algorithms, such as algorithms for decoding compressed digital audio and video data. As the complexity of these algorithms increases, so too does the memory usage for storing the algorithms.
Generally, instructions to be executed are stored in a dedicated instruction cache of a microprocessor. For large algorithms, the sets of instructions become too large to fit on the dedicated instruction cache. This capacity deficit results in cycles of loading a subset of the instructions into the dedicated instruction cache from non-volatile memory, executing instructions of the subset and swapping the subset out for the next subset of instructions. In addition to the time required to load instructions, writing instructions from memory to the cache occupies the system bus. Frequently accessing non-volatile memory also reduces the throughput of data into the microprocessor.
In real-time processing, such as decoding audio and video for playback, these delays can decrease the performance of a device. To reduce memory access latency, designers have turned to small intermediate level caches to retrieve and store frequently used instruction sets for easier access by the microprocessor. These small intermediate level caches are referred to as level 2 or level 3 caches and are typically static random access memory (SRAM) devices located close to the microprocessor. However, SRAM is expensive and increases product cost.
To manage access to instruction sets and non-instruction data, typical systems rely on manual overlays in which a programmer manages memory by programmatically moving code into a desired location prior to use. Often, instruction sets are overwritten as new instruction sets are used. Such systems rely on the programmer to correctly allocate memory and move instructions and non-instruction data to desired locations prior to accessing the instructions and non-instruction data. For large programs and systems running many tasks, such memory management is difficult, especially when more than one programmer is coding system instructions.
Alternatively, systems may use a memory management unit. Each task, such as word processing, spreadsheets, and user interface interaction, is provided with a virtual memory space. As the processor accesses a particular virtual memory space to perform a particular task, the instructions and non-instruction data associated with that task are moved to physical memory locations more easily accessed by the processor, such as to level 2 cache. The memory management unit maintains a record of the location of the instructions and non-instruction data in the physical memory. Instructions and non-instruction data associated with tasks other than the particular task being executed may be written to non-volatile storage, such as hard drives, or may be written to higher-level cache. However, task specific virtual addressing as implemented in traditional memory management units results in a significant amount of disk access and, as a result, large power consumption. Frequently accessing non-volatile storage can also lead to delays when switching between tasks. In another embodiment, large higher-level caches, such as SRAM, are used. These higher-level caches are typically expensive and consume power. As such, typical memory management unit implementation is unsuitable for portable devices and other devices with limited access to power.
As such, an improved system and method of memory management would be desirable.
The use of the same reference symbols in different drawings indicates similar or identical items.